1. Field of the Invention
The present invention relates to a large-scale integrated circuit (LSI) inspection method and a defect inspection data analysis apparatus for judging whether a semiconductor device (chip), such as an LSI, formed on a wafer is a conforming or non-conforming article.
2. Description of Related Art
FIG. 4 is a view used to explain the flow of an inspection process by a conventional LSI inspection method. Initially, as shown in FIG. 4, a defect inspection is performed on a wafer each time processing is completed in each of predetermined process steps among a plurality of process steps in the front-end process. The defect inspections are performed to judge whether semiconductor manufacturing equipment that performs processing in the process steps is operating normally or not. For example, upon judgment that a number of foreign substances or the like are adhering onto a wafer, the semiconductor manufacturing equipment is suspended and an inspection, cleaning, etc. thereof are performed.
When a wafer is completed upon completion of the front-end process, a wafer test is run subsequently. As shown in FIG. 4, the wafer test includes an element parameter measurement test, a wafer B/I (Burn-In) test, and an electric property test (see, for example, Patent Document 1). In the element parameter measurement test, basic parameters of an element are measured to confirm that an element having desired properties has been formed. Normally, several elements are selected from a clearance (scribe region) between particular chips, and this test is run only on the selected elements.
The wafer B/I (Burn-In) test is run to ensure the reliability of each chip by accelerating deterioration of potential defects with application of electrical or thermal stress to the wafer in making a chip having such a potential defect completely defective. Also, the electric property test is a test by which an electric property of each chip formed on the wafer is tested to judge whether each chip is defective or non-defective on the basis of the test result.
In a case where the product is sold in the form of a wafer, the wafer is delivered after the wafer test is completed, together with a wafer map indicating the judging result as to whether each chip is a conforming or non-conforming article.
Herein, a published Japanese translation of PCT International Application No. 2001-526833 is cited as Patent Document 1.
Incidentally, the electric property test is conventionally run on all the chips formed on the wafer, and there is a problem that the test takes a long time. In particular, the number of elements contained in one chip keeps increasing in these days, and for this reason, the test time tends to extend further. Also, the reliability level of each chip is conventionally enhanced by running the wafer B/I test. However, running the wafer B/I test does not necessarily succeed in making all the chips having potential defects defective, and there is a case where a chip having a potential defect is judged erroneously as being a conforming article.